1. Field of the Invention
The present invention relates to dual-port memories, that is, memories including separate inputs and outputs, and more particularly to first-in/first-out (FIFO) memories.
2. Discussion of the Related Art
FIG. 1 partially represents a conventional dual-port memory structure. This memory includes dual-port memory cells 10 disposed in columns. As shown, each cell 10 includes, for example, two head-to-tail connected inverters 10-1. Each inverter includes a pair of complementary output (N and P-channel MOS) transistors. The input and the output of the cell respectively correspond to the input and the output of a first inverter. The second inverter, whose output is connected to the input of the memory cell, includes output transistors that are more resistive than the transistors of the first inverter, so as to limit current consumption during a write cycle in the cell.
With each column of cells is associated an input bit line Bi and an output bit line Bo. The input of each cell 10 of a column is connected to the corresponding input line Bi through an N-channel MOS transistor M1. The output of each cell 10 of a column is connected to the corresponding output line Bo through an N-channel MOS transistor M2. The gates of transistors M1 of a same row of cells are connected to a write line W and the gates of transistors M2 of a same row of cells are connected to a read line R.
Each output line Bo is connected to a high supply voltage Vdd through a P-channel MOS transistor MP1, referred to as a precharge transistor. Each output line Bo is connected to an output Bo1 of the memory through successively an N-channel MOS transistor M3, a latch 12 constituted by head-to-tail connected inverters, and a three-state gate 14.
Transistors MP1 and M3 are controlled by a read-column signal RC. The three-state gates 14 are controlled by an enable signal EN that may be equal to signal RC or fixed by an external device, such as a microprocessor, that reads the memory. The precharge transistors MP1 can also be N-channel transistors; if they are N-channel transistors, they are controlled by the logic complement of signal RC.
In a common conventional configuration, the input lines Bi are directly connected, or through buffers (not shown), to respective lines of an input data bus Di. The outputs Bo1 of the memory are connected to respective lines of an output bus Do. Thus, with n-line data buses Di and Do are associated n-column dual-port memories.
The write lines W and read lines R are controlled by an address decoder (not shown). To write data in the memory, the device controlling the input bus Di presents data on bus Di, issues an address (on an address bus, not shown) that selects one of the rows of the cells, and asserts a write-column line WC (not shown in FIG. 1).
To read data out of the memory, a device that controls the bus Do issues an address that selects one of the rows of the cells, asserts the read-column line RC, and asserts line EN.
Dual-port memories such as the one of FIG. 1 are often used in FIFO memories. A FIFO does not have an address bus. To read in a FIFO, the read-column line RC is asserted and the data that the memory then presents at its output (Bo1) is read. To write in the FIFO, the write-column line WC is asserted and the data to write is presented at its input (Bi).
A FIFO generally includes a dual-port memory such as the one of FIG. 1 with an address decoder, the addresses being provided by a relatively complex control circuit that manages the FIFO mechanism as a function of the write-column signals WC and read-column signals RC provided externally.
FIG. 2 shows the waveform of various signals in the structure of FIG. 1 during successively reading a "0" in a first cell and reading twice a "1" in a second cell. At successive times t1, t2 and t3, it is decided to carry out the above read cycles.
At time t1, the read-column line RC and a line R1 that corresponds to one of the read lines R are asserted. Transistor M2 is turned on and transmits the output of cell 10 to the output line Bo. Transistor MP1 is off and line Bo is not forced to voltage Vdd. The cell 10 that is read contains a "0", which means that the input of the cell is at "0", whereas its output is at "1". Thus, line Bo remains at "1". The transistor M3 is turned on and transmits the state "1" of line Bo to the input of latch 12 that inverses this state. Thus, the output Bo1 and the corresponding line of bus Do, are set to or remain at "0". The lines RC and R1 are disabled before time t2, which causes the precharge transistors MP1 to turn on and the output transistors M3 to be turned off.
At time t2, it is decided to read a "1" in a second memory cell. Line PC is again asserted and a line R2 corresponding to another read line R is asserted. This time, the output of the cell 10 that is read is at "0". Line Bo slowly passes from Vdd to 0 while discharging toward the output of cell 10 through transistor M2, the output of cell 10 being forced to ground by a transistor of the cell. Latch 12 switches only when the state of line Bo reaches a switching threshold Vt at time t2s. Thus, the output Bo1 changes to "1" slightly after time t2. Before time t3, lines RC and R2 are disabled, which causes the output lines Bo to be reset to "1".
At time t3, the same cell as at time t2 is read again. Lines RC and R2 are again asserted. As at time t2, line Bo is progressively discharged from Vdd to 0 through transistor M2 toward the output of the cell that is being read. However, between time t3 and time t3s, when the state of line Bo reaches the threshold voltage Vt, latch 12, whose input was at "0", switches at time t3, and switches again at time t3s. This causes, as shown, an undesired passage through "0" of output Bo1 between times t3 and t3s.
FIG. 2 also shows the waveform Bi.sub.x of an input line of a second dual-port memory whose input would be connected to bus Do. The state of line Bi.sub.x varies in the same manner as the corresponding output Bo1.
As is the case for all CMOS circuits, a memory such as the one of FIG. 1 consumes current only during transitions of its internal signals. Thus, the current consumption of such a memory is unduly increased due to undesired passage through "0" of output Do1 between two read cycles of a "1". Furthermore, the current consumption increases with the length of the lines on which these signals transit. Thus, the current consumption becomes significantly high if the output of a first dual-port memory is connected to the inputs of a plurality of additional dual-port memories.